Position Details: Director Technology/Technical Lead – Physical Design
Location:
Bangalore (No location constraint), karnataka
Openings:
1
Salary Range:
Description:
Location
Bangalore, Hyderabad, Noida
Summary
Provide technical leadership for team working on state-of-the-art SOCs at cutting edge FinFET technology nodes for various high profile startups as well as leading semiconductor companies around the world.
This position is for a senior-level Physical design leader who will
Lead the implementation of a complex SoCs
Build and guide a team of implementation engineers
Work hands-on on critical tasks as and when needed
Own the RTL-GDS2 implementation flows, methodologies and execution of SoCs
Experience:
Experience in all phases of the IC design process from RTL->GDS2
Physical implementation of SoC/Full-chip-level and/or high-speed ARM cores, DSP and GPU cores
Experience in high-speed, low-power, mixed-signal SoC’s is a plus
Preferably worked on 5nm/7nm/12nm/14nm/16nm nodes at the major foundries
Experience in developing PNR methodology/flow to and supporting a larger PD team
Experience in floorplanning, clocking & power network architecture and design
Experience in low-power implementation using UPF/CPF power intent flow
Experience in I/O Ring, RDL routing, bumps and other top-level design considerations
Experience in LVS/DRC/ERC, EMIR (static & dynamic), LEC and Reliability sign-off checks
Experience in STA analysis, timing closure and defining chip sign-off criterion
Thorough understanding of digital design, timing analysis, and DFT
Good understanding of foundation IP components – Standard cells, SRAMs etc.